1. Field of the Invention
The present invention relates to signal processing, and, in particular, to controlling phase in a delay loop, such as a voltage-controlled delay loop (VCDL) used to generate multiple sampling clock signals for sampling received data.
2. Description of the Related Art
Certain receivers that perform clock-and-data recovery (CDR) processing on their received signals employ a voltage-controlled delay loop having a plurality of sequentially arranged delay elements that generate multiple sampling clock signals used to sample data in the received signal. In order for such a receiver to operate properly, (1) the phases of the sampling clock signals should be phase-aligned with the data in the received signal and (2) the overall (i.e., bulk) delay of the VCDL should be the same as the period of the local reference clock signal used by the VCDL to generate the sampling clock signals. To achieve those goals, such receivers are typically designed with control loops that adjust the operations of the VCDL to ensure proper receiver operations. Failure to adequately control the VCDLs in such receivers can result in jitter in the sampling clock signals, which can adversely affect the results of the CDR processing.